Noise isolation between unrelated circuits on an integrated circuit (IC) is highly desirable. This is particularly true when high power circuits and low power circuits are on the same IC. For example, low power circuits may process minimal signals (&lt;10 mV) and cannot tolerate interference generated by high power circuits on the same IC. FIG. 1 illustrates one of the mechanisms in which coupling occurs between separate functions on the same IC. For example, when digital circuitry 10 switches between high and low states, the change in the inputs and outputs of digital circuitry 10 creates current impulses that are injected into the common substrate 15 via parasitic capacitance C2. C2 represents the total parasitic capacitance that exists between digital circuitry 10 and the common substrate 15. Transistors within digital circuitry 10 may be used to construct logic devices, such as inverters, NOR gates and AND gates that all contribute to the parasitic capacitance C2 that allows current to be injected into the common substrate 15 from digital circuitry 10. The current impulses from the digital circuitry 10, that are injected in the substrate 15, flow through substrate 15. Substrate 15 has a resistance that is represented by resistors R1, R2 and R3 between digital circuitry 10 and ground connections 20, 25 of the IC.
The current flow that is coupled through resistance R1 from digital circuitry 10 via parasitic capacitance C2 causes voltage noise that is coupled to analog circuitry 30 through parasitic capacitance C1. This noise coupling mechanism causes noise within analog circuitry 30 which limits the minimal signal voltages that can be processed by analog circuitry 30 when analog circuitry 30 is placed on the same IC (same substrate) as digital circuitry 10.
The distribution of the current flow, and hence the amount of coupled noise, is dependent on the values of resistances of R1, R2, and R3. If R1 is decreased relative to R2 and R3, more noise voltage is coupled to analog circuitry 30. When epitaxial wafers are used, the substrate normally has a lower resistance so that cross-talk problems are increased.
Currently, two basic substrate architectures exist for standard CMOS processing: bulk substrate wafers and epitaxial layered wafers. Bulk substrate wafers consist of silicon that is uniformly doped to a constant carrier concentration. Epitaxial layered wafers have a base of substrate layer that is a heavily doped layer and a lightly doped epitaxial layer. The light doping of the epitaxial layer emulates the surface background carrier concentration similar to that of the bulk substrate wafers. The heavily doped substrate layer provides a low impedance connection (R1), and thus more severe noise coupling occurs between analog circuitry 30 and digital circuitry 10.
Many alternatives exist to decrease the noise coupling through a common substrate. One alternative is to manufacture digital and analog circuits on separate ICs. This adds cost due to separate packaging and increased pin counts. Another alternative utilizes special processing steps, such as dielectric or junction isolation, that physically isolate unrelated circuits. However, these steps are costly compared to standard CMOS processes. Other alternatives rely on circuit design techniques, such as current-mode logic, or spacing of the unrelated circuits, but circuit noise isolation is still difficult to achieve using these alternatives.
It is against this background, and the limitations and problems associated therewith, that the present invention has been developed.